1. Field of the Invention
The present invention relates to a memory device and, more particularly, to a read only memory device.
2. Description of Related Art
A memory cell array of a conventional read only memory device includes a read only memory cell array for storing data and programs, a reference memory cell array for generating a reference voltage, and a dummy memory cell array for generating a sense amplifier enable signal.
A reference voltage generated from the reference memory cell array is set at an intermediate level between a “high” level and a “low” level. The reference voltage is applied to bit lines of the read only memory cell array. A signal generated from the dummy memory cell array generates a sense amplifier enable signal for enabling the sense amplifier.
In the conventional read only memory device, however, the reference memory cell array connected to each of word lines and NMOS transistors of the dummy memory cell array have different characteristics according to process distributions. These process distribution allow for the generation of the reference voltage by the reference memory cell array and generation of the sense amplifier enable signal by the dummy memory cell array at different times. The result is higher data read errors. Accordingly, a need remains for an improved read only memory device.